Design and Implement Inverter using Different Adiabatic logics

Author (s):

  1. Pragati Upadhyay, SSTC, SSGI (FET), Bhilai, India,
  2. Vishal Moyal, SSTC, SSGI (FET), Bhilai, India


This paper describes an energy efficient technique with different kind of adiabatic logic. Inverter can be designed using Complementary metal oxide semiconductor (CMOS) logic, Positive Feedback Adiabatic Logic (PFAL) and Two- Phase Adiabatic Static Clocked Logic (2PASCL). In this paper we have propose adiabatic logic inverter circuit and compare this circuit with the PFAL and 2PASCL logic. Adiabatic logic is a low power circuit, which is a reversible logic it is used to conserve energy. The proposed circuit compares in terms of power consumption using conventional static CMOS and PFAL logic. All design is to be simulated using TANNER EDA tool V15.0. Simulation will be done at BSIM4 90nm technologies.

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