FPGA based hardware design flow of distributed arithmetic (DA) based 2D Discrete Wavelet Transform (DWT) for the proposed image compression algorithm


Author (s):

  1. D. U. Shah, R. K. University, Rajkot, Gujarat, INDIA, devang.shah@rku.ac.in
  2. Dr. C. H. Vithalani, Government Engineering College, Rajkot, Gujarat, India

Abstract:

The need for an efficient technique for compression of images is ever increasing because, the raw images need large amounts of disk space seems to be a big disadvantage during transmission and storage. Even though, there are so many compression techniques already present, a better technique which is faster, memory efficient and simple surely suits the requirements of the user. We have planned to design the hardware design flow of distributed arithmetic (DA) based 2-D Discrete Wavelet Transform (DWT) for the proposed image compression algorithm. According to, an effective 2-D DWT will be performed on input image using well-known Distributed Arithmetic (DA) technique, which exploits the LUT-based FPGA structure to build multiplier-less filter bank, the main component in a DWT structure. After computing the DWT, the suitable wavelet co-efficient are selected and then, applied DPCM (Differential pulse-code modulation) that is a transformation for increasing the compressibility of an image. Finally, the transformed image is given to Huffman-encoder that is designed by merging the lowest probable symbols in such a way that, the images will get compressed. For implementation, the DA-based wavelet is modeled in simulink and tested. The verilog source code is developed for the algorithm. All the modules are simulated in Xilinx tool and the final design is verified with verilog test benches. The final design is implemented in Xilinx Atlys Spartan 6 FPGA Kit.

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